Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures

This paper presents a comprehensive thermal scaling analysis of multilevel interconnects in deep nanometer scale CMOS technologies based on technological, structural, and material data from ITRS ’03 [1]. Numerical simulations have been performed using three-dimensional (3-D) electrothermal finite element methods (FEM), combined with accurate calculations of temperatureand size-dependent Cu resistivity and thermal conductivity of low-k interlayer dielectrics (ILD) based on fully physical models. The simulations also incorporate various scaling factors from fundamental material level to system level: the via-density dependent effective ILD thermal conductivity, the hierarchically varying RMS current stress based on SPICE simulations, and the thermal resistance of flip-chip package. It is shown that even after considering densely embedded vias, the interconnect temperature is expected to increase significantly with scaling, due to increasing surface and grain boundary contributions to metal resistivity and decreasing ILD thermal conductivity.